Probing wire bond issues for bonding over Cu/low-K dielectric materials

OVERVIEW: The introduction of low-k and ultralow-k dielectric films in copper-interconnect structures presents serious challenges in test, assembly, and packaging of advanced devices. Low-k films support higher circuit speeds and enable smaller feature sizes by increasing the insulation capability around copper interconnects, but compared to previous generations of silicon-dioxide dielectric layers, the new materials have substantially weaker mechanical properties and reduced thermal conductivity. Fragile low-k materials increase the risk of damage to finished devices in wafer probe test and high-speed final assembly processes. Compounding the situation is the simultaneous introduction of copper interconnects and ultra-fine pitch pad layouts. Experiments on wafer designs with different pad structures have been conducted to determine optimal structures and other factors for improved process robustness in probe test and wire bonding.